Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

Jean-Luc Danger; Risa yashiro; Tarik Graba; yves Mathieu; Abdelmalek Si-Merabet; Kazuo Sakiyama; Noriyuki Miura; Makoto Nagata

Conference papers

Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

Jean-Luc Danger ^{1, 2, 3} Risa yashiro ⁴ Tarik Graba ^{1, 2, 3} yves Mathieu ^{5, 2, 3} Abdelmalek Si-Merabet ^{1, 2, 3} Kazuo Sakiyama ⁴ Noriyuki Miura ⁶ Makoto Nagata ^{7, 6}

1 LTCI - Laboratoire Traitement et Communication de l'Information

2 COMELEC - Département Communications & Electronique

3 SSH - Secure and Safe Hardware

LTCI - Laboratoire Traitement et Communication de l'Information

4 The University of Electro-Communications [Tokyo]

5 LTCI - Laboratoire Traitement et Communication de l'Information

6 Kobe University

7 Dep. of Computer and Engineering

Document type :

Conference papers

Domain :

Computer Science [cs] / Hardware Architecture [cs.AR]

Computer Science [cs] / Computer Arithmetic

Computer Science [cs] / Cryptography and Security [cs.CR]

Computer Science [cs] / Digital Libraries [cs.DL]

Computer Science [cs] / Modeling and Simulation

Engineering Sciences [physics] / Electronics

Complete list of metadata

https://hal.telecom-paris.fr/hal-02271687
Contributor : Tarik Graba Connect in order to contact the contributor
Submitted on : Tuesday, August 27, 2019 - 10:33:21 AM
Last modification on : Wednesday, March 23, 2022 - 10:18:02 AM

Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

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Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

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