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Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

Jean-Luc Danger 1, 2, 3 Risa Yashiro 4 Tarik Graba 1, 2, 3 Yves Mathieu 5, 2, 3 Abdelmalek Si-Merabet 1, 2, 3 Kazuo Sakiyama 4 Noriyuki Miura 6 Makoto Nagata 7, 6
1 LTCI - Laboratoire Traitement et Communication de l'Information
2 COMELEC - Département Communications & Electronique
3 SSH - Secure and Safe Hardware
LTCI - Laboratoire Traitement et Communication de l'Information
4 The University of Electro-Communications [Tokyo]
5 LTCI - Laboratoire Traitement et Communication de l'Information
6 Kobe University
7 Dep. of Computer and Engineering
Document type :
Conference papers
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https://hal.telecom-paris.fr/hal-02271687
Contributor : Tarik Graba Connect in order to contact the contributor
Submitted on : Tuesday, August 27, 2019 - 10:33:21 AM
Last modification on : Thursday, November 18, 2021 - 1:02:06 PM

Identifiers

  • HAL Id : hal-02271687, version 1

Collections

LTCI | CNRS | PARISTECH | INSTITUT-TELECOM | COMELEC | SSH | TDS-MACS

Citation

Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, et al.. Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. 2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.508-515. ⟨hal-02271687⟩

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