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Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

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https://hal.telecom-paris.fr/hal-02271687
Contributor : Tarik Graba <>
Submitted on : Tuesday, August 27, 2019 - 10:33:21 AM
Last modification on : Tuesday, September 21, 2021 - 2:16:05 PM

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  • HAL Id : hal-02271687, version 1

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Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, et al.. Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. 2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.508-515. ⟨hal-02271687⟩

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