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Calibrating a predictive cache emulator for SoC design

Abstract : Pre-fetching in a memory hierarchy is known to alleviate the “memory wall” paradigm but its use is impeded because of the difficulty to estimate efficiency when used in a complex system such as a SoC (System on Chip) or NoC (Network on Chip). Therefore, some methods are needed to evaluate the benefit of pre-fetching at the earliest possible stage in a design flow to help the designer choose architectural parameters or transform the application algorithm. In this paper we show that the emulation platform implementing the nD-AP Cache (n-Dimensional Adaptive and Predictive Cache) allows to perform a platform-independent measurement of this cache efficiency. The nD-AP Cache performs pre-fetching in multidimensional arrays which are commonly used in image processing and multimedia applications. The obtained metric can be used to extrapolate the cache performance in a much broader system configuration. The method to compute this metric is the calibration process. The performed benchmarks show that the calibration process is confident. Also, we measured that the nD-AP Cache is two times faster than a standard PowerPC 2-way set associative cache in the context of an image processing kernel.
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https://hal.telecom-paris.fr/hal-02278686
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Submitted on : Wednesday, September 4, 2019 - 3:09:32 PM
Last modification on : Monday, March 28, 2022 - 10:34:01 AM

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Stéphane Mancini, Lionel Pierrefeu, Zahir Larabi, yves Mathieu. Calibrating a predictive cache emulator for SoC design. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2010, Anaheim, Californie, United States. pp.273-280, ⟨10.1109/AHS.2010.5546246⟩. ⟨hal-02278686⟩

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