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Journal articles
Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks
N. Selmane 1
Author
Shivam Bhasin 2, 3
Author
Sylvain Guilley 2, 3
Mail :
Author IdHAL : sylvain-guilley ORCID : https://orcid.org/0000-0002-5044-3534
Jean-Luc Danger 2, 3
Mail : Site :
Author IdHAL : jeanluc-danger
1
LTCI - Laboratoire Traitement et Communication de l'Information (46 rue Barrault F-75634 Paris Cedex 13 - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
- CNRS - Centre National de la Recherche Scientifique : UMR5141 (France)
2
SSH - Secure and Safe Hardware (46 rue Barrault
75013 Paris - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (46 rue Barrault F-75634 Paris Cedex 13 - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
- Télécom Paris (19 Place Marguerite Perey 91120 Palaiseau - France)
3
COMELEC - Département Communications & Electronique (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
Document type :
Journal articles
Domain :
Complete list of metadatas
https://hal.telecom-paris.fr/hal-02286262
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 3:33:07 PM
Last modification on : Friday, July 31, 2020 - 11:28:08 AM
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 3:33:07 PM
Last modification on : Friday, July 31, 2020 - 11:28:08 AM
Identifiers
- HAL Id : hal-02286262, version 1
- DOI : 10.1049/iet-ifs.2010.0238
Citation
N. Selmane, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger. Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks. Information Security, IET, 2011, 5 (4), pp.181-190. ⟨10.1049/iet-ifs.2010.0238⟩. ⟨hal-02286262⟩
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