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A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems

Hao Cai 1, 2 J. F. Naviner H. Petit 3, 2 
1 SSH - Secure and Safe Hardware
LTCI - Laboratoire Traitement et Communication de l'Information
2 COMELEC - Département Communications & Electronique
3 C2S - Circuits et Systèmes de Communication
LTCI - Laboratoire Traitement et Communication de l'Information
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Journal articles
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https://hal.telecom-paris.fr/hal-02286422
Contributor : TelecomParis HAL Connect in order to contact the contributor
Submitted on : Friday, September 13, 2019 - 3:43:41 PM
Last modification on : Tuesday, October 19, 2021 - 11:16:43 AM

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  • HAL Id : hal-02286422, version 1

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INSTITUT-TELECOM | PARISTECH | LTCI | COMELEC | C2S-CIRCUITS | SSH

Citation

Hao Cai, J. F. Naviner, H. Petit. A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems. Journal of Low Power Electronics, 2012, 8 (5). ⟨hal-02286422⟩

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