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Journal articles
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation
Sho Endo
Yang Li
Naofumi Homma
1, 2
Kazuo Sakiyama
Kazuo Ohta
Daisuke Fujimoto
Makoto Nagata
Toshihiro Katashita
Jean-Luc Danger
1, 2
Takafumi Aoki
Jean-Luc Danger 1, 2
Author IdHAL : jeanluc-danger ORCID : https://orcid.org/0000-0001-5063-7964
Takafumi Aoki
Author
1
SSH - Secure and Safe Hardware (Télécom Paris 19 Place Marguerite Perey 91120 Palaiseau - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (Télécom Paris 19 Place Marguerite Perey 91120 PALAISEAU - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
- Télécom Paris (19 Place Marguerite Perey 91120 Palaiseau - France)
2
COMELEC - Département Communications & Electronique (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
Document type :
Journal articles
Domain :
Complete list of metadata
https://hal.telecom-paris.fr/hal-02287186
Contributor : Telecomparis Hal Connect in order to contact the contributor
Submitted on : Friday, September 13, 2019 - 4:41:22 PM
Last modification on : Thursday, November 18, 2021 - 1:02:02 PM
Contributor : Telecomparis Hal Connect in order to contact the contributor
Submitted on : Friday, September 13, 2019 - 4:41:22 PM
Last modification on : Thursday, November 18, 2021 - 1:02:02 PM
Identifiers
- HAL Id : hal-02287186, version 1
- DOI : 10.1109/TVLSI.2014.2339892
Collections
LTCI | PARISTECH | INSTITUT-TELECOM | COMELEC | SSH
Citation
Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, et al.. A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2015, ⟨10.1109/TVLSI.2014.2339892⟩. ⟨hal-02287186⟩
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