Fully Digital Feedforward Background Calibration Of Clock Skews For Sub-sampling TIADCs Using The Polyphase Decomposition

Han Le Duc; D. M. Nguyen; Chadi Jabbour; Patricia Desgreys; Olivier Jamin; V. T. Nguyen

doi:10.1109/TCSI.2016.2645978

Journal articles

Fully Digital Feedforward Background Calibration Of Clock Skews For Sub-sampling TIADCs Using The Polyphase Decomposition

Han Le Duc ^{1, 2} D. M. Nguyen Chadi Jabbour ^{1, 2} Patricia Desgreys ^{1, 2} Olivier Jamin ^{3, 1, 2} V. T. Nguyen ^{1, 2}

1 C2S - Circuits et Systèmes de Communication

LTCI - Laboratoire Traitement et Communication de l'Information

2 COMELEC - Département Communications & Electronique

3 NXP Semiconductors

Keywords : All-digital feedforward calibration Subsampling and undersampling TIADCs FPGA/ASIC implementation polyphase ﬁltering.

Document type :

Journal articles

Domain :

Engineering Sciences [physics] / Electronics

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Submitted on : Friday, September 13, 2019 - 4:57:08 PM
Last modification on : Friday, July 31, 2020 - 11:28:04 AM

Fully Digital Feedforward Background Calibration Of Clock Skews For Sub-sampling TIADCs Using The Polyphase Decomposition

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Fully Digital Feedforward Background Calibration Of Clock Skews For Sub-sampling TIADCs Using The Polyphase Decomposition

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