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Journal articles
Efficient reliability evaluation methodologies for combinational circuits
Hao Cai
1, 2
Kaikai Liu
1, 2
Lirida Alves de Barros Naviner
1, 2
You Wang
1, 2
Mariem Slimani
1, 2
Jean-François Naviner
Hao Cai 1, 2
Author
Kaikai Liu 1, 2
Author
Lirida Alves de Barros Naviner 1, 2
Author
You Wang 1, 2
Author
Mariem Slimani 1, 2
Author
Jean-François Naviner
Author
1
SSH - Secure and Safe Hardware (46 rue Barrault
75013 Paris - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (46 rue Barrault F-75634 Paris Cedex 13 - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
2
COMELEC - Département Communications & Electronique (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
Document type :
Journal articles
Complete list of metadatas
https://hal.telecom-paris.fr/hal-02287474
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 4:59:52 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:53 PM
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 4:59:52 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:53 PM
Identifiers
- HAL Id : hal-02287474, version 1
Collections
LTCI | PARISTECH | INSTITUT-TELECOM | COMELEC | SSH | UNIV-PARIS-SACLAY
Citation
Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner, You Wang, Mariem Slimani, et al.. Efficient reliability evaluation methodologies for combinational circuits. Microelectronics Reliability, 2016, 64. ⟨hal-02287474⟩
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