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Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits

Francisco Veirano Lirida Alves de Barros Naviner 1, 2 Fernando Silveira 
1 SSH - Secure and Safe Hardware
LTCI - Laboratoire Traitement et Communication de l'Information
2 COMELEC - Département Communications & Electronique
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https://hal.telecom-paris.fr/hal-02287635
Contributor : TelecomParis HAL Connect in order to contact the contributor
Submitted on : Friday, September 13, 2019 - 5:10:00 PM
Last modification on : Friday, January 7, 2022 - 5:06:04 PM

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  • HAL Id : hal-02287635, version 1

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INSTITUT-TELECOM | PARISTECH | UNIV-PARIS-SACLAY | LTCI | COMELEC | SSH

Citation

Francisco Veirano, Lirida Alves de Barros Naviner, Fernando Silveira. Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2017. ⟨hal-02287635⟩

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