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Journal articles
Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits
1
SSH - Secure and Safe Hardware (46 rue Barrault
75013 Paris - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (46 rue Barrault F-75634 Paris Cedex 13 - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
2
COMELEC - Département Communications & Electronique (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
Document type :
Journal articles
Complete list of metadatas
https://hal.telecom-paris.fr/hal-02287635
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 5:10:00 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:54 PM
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 5:10:00 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:54 PM
Identifiers
- HAL Id : hal-02287635, version 1
Collections
LTCI | PARISTECH | INSTITUT-TELECOM | COMELEC | SSH | UNIV-PARIS-SACLAY
Citation
Francisco Veirano, Lirida Alves de Barros Naviner, Fernando Silveira. Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017. ⟨hal-02287635⟩
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