Asymmetrical Length Biasing for Energy Efficient Digital Circuits

Francisco Veirano; Lirida Alves de Barros Naviner; Fernando Silveira

Conference Papers Year : 2017

Asymmetrical Length Biasing for Energy Efficient Digital Circuits

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Francisco Veirano

Function : Author

Lirida Alves de Barros Naviner

Function : Author
PersonId : 737026
IdHAL : lirida-naviner
ORCID : 0000-0002-6320-4153

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Département Communications & Electronique

Fernando Silveira

Function : Author
PersonId : 759154
ORCID : 0000-0001-9700-7521

Domains

Engineering Sciences [physics] Micro and nanotechnologies/Microelectronics Engineering Sciences [physics] Electronics

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Submitted on : Friday, September 13, 2019-5:10:05 PM

Last modification on : Tuesday, February 28, 2023-3:36:25 PM

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hal-02287637 , version 1 (13-09-2019)

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HAL Id : hal-02287637 , version 1

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Francisco Veirano, Lirida Alves de Barros Naviner, Fernando Silveira. Asymmetrical Length Biasing for Energy Efficient Digital Circuits. IEEE Latin American Symposium on Circuits and Systems, Feb 2017, Bariloche, Argentina. ⟨hal-02287637⟩

Asymmetrical Length Biasing for Energy Efficient Digital Circuits

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