 |
- Home
- Submit
-
Browse
- By laboratory
- By department
-
By researchteam
- ACES - Autonomic and Critical Embedded Systems
- CCN - Cybersecurity for Communication and Networking
- COMNUM - Communications numériques
- LinkC2S - Circuits et Systèmes de communication
- DIG - Data, Intelligence and Graphs
- DIVA - Design, Interaction, Visualization and Applications
- ECOGE - Economie Gestion
- GTO - Télécommunications Optiques
- IMAGES - Image, Modélisation, Analyse, GEométrie, Synthèse
- IQA - Information Quantique et Applications
- LabSoC - System on Chip
- MC2 - Mathématiques discrètes, Codage et Cryptographie
- MM- Multimédia
- RFM2 - Radio-Fréquences Microondes et Ondes Millimétriques
- RMS - Réseaux, Mobilité et Services
- S2A - Signal, Statistique et Apprentissage
- SID - Sociologie, Information-Communication Design
- SPE - Sociologie, Psychologie ergonomique
- SSH - Secure and Safe Hardware
- By doctype
- Browse by author
- Search
Conference papers
Exploring the Feasibility of Selective Hardening for Combinational Logic
Samuel Nascimento Pagliarini
1, 2
Gutemberg Gonçalves dos Santos Jr
Lirida Alves de Barros Naviner
1, 2
Jean-François Naviner
3
Samuel Nascimento Pagliarini 1, 2
Author
Lirida Alves de Barros Naviner 1, 2
Author
Jean-François Naviner 3
Author
1
SSH - Secure and Safe Hardware (46 rue Barrault
75013 Paris - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (46 rue Barrault F-75634 Paris Cedex 13 - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
2
COMELEC - Département Communications & Electronique (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
3
LTCI - Laboratoire Traitement et Communication de l'Information (46 rue Barrault F-75634 Paris Cedex 13 - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
- CNRS - Centre National de la Recherche Scientifique : UMR5141 (France)
Document type :
Conference papers
Complete list of metadatas
https://hal.telecom-paris.fr/hal-02288323
Contributor : Telecomparis Hal <>
Submitted on : Saturday, September 14, 2019 - 6:41:28 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:54 PM
Contributor : Telecomparis Hal <>
Submitted on : Saturday, September 14, 2019 - 6:41:28 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:54 PM
Identifiers
- HAL Id : hal-02288323, version 1
Citation
Samuel Nascimento Pagliarini, Gutemberg Gonçalves dos Santos Jr, Lirida Alves de Barros Naviner, Jean-François Naviner. Exploring the Feasibility of Selective Hardening for Combinational Logic. European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Oct 2012, Cagliari, Italy. ⟨hal-02288323⟩
Metrics
Record views
