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Conference papers
A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor
Noriyuki Miura
Kohei Matsuda
Karol Myszkowski
Makoto Nagata
Shivam Bhasin
1, 2
Ville Yli-Mayry
Naofumi Homma
1, 2
Yves Mathieu
1, 2
Tarik Graba
1, 2
Jean-Luc Danger
1, 2
Shivam Bhasin 1, 2
Author
Ville Yli-Mayry
Author
Naofumi Homma 1, 2
Author
Yves Mathieu 1, 2
Mail :
Author IdHAL : yves-mathieu
Tarik Graba 1, 2
Mail :
Author IdHAL : tarikgraba
Jean-Luc Danger 1, 2
Mail : Site :
Author IdHAL : jeanluc-danger
1
SSH - Secure and Safe Hardware (46 rue Barrault
75013 Paris - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (46 rue Barrault F-75634 Paris Cedex 13 - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
2
COMELEC - Département Communications & Electronique (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
Abstract : An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational- logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289µm 2 /Gb/s of ultra-light-weight cryptographic performance.
Document type :
Conference papers
Domain :
Complete list of metadatas
https://hal.telecom-paris.fr/hal-02288491
Contributor : Telecomparis Hal <>
Submitted on : Saturday, September 14, 2019 - 6:53:07 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:54 PM
Contributor : Telecomparis Hal <>
Submitted on : Saturday, September 14, 2019 - 6:53:07 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:54 PM
Identifiers
- HAL Id : hal-02288491, version 1
Collections
LTCI | PARISTECH | INSTITUT-TELECOM | COMELEC | SSH | UNIV-PARIS-SACLAY
Citation
Noriyuki Miura, Kohei Matsuda, Karol Myszkowski, Makoto Nagata, Shivam Bhasin, et al.. A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor. Symposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267. ⟨hal-02288491⟩
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