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A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor

Noriyuki Miura Kohei Matsuda Karol Myszkowski Makoto Nagata Shivam Bhasin 1, 2 Ville Yli-Mayry Naofumi Homma 1, 2 Yves Mathieu 1, 2 Tarik Graba 1, 2 Jean-Luc Danger 1, 2
1 SSH - Secure and Safe Hardware
LTCI - Laboratoire Traitement et Communication de l'Information
2 COMELEC - Département Communications & Electronique
Abstract : An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational- logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289µm 2 /Gb/s of ultra-light-weight cryptographic performance.
Keywords : cryptographic circuits Prince FDSOI
Document type :
Conference papers
Complete list of metadatas
https://hal.telecom-paris.fr/hal-02288491
Contributor : Telecomparis Hal <>
Submitted on : Saturday, September 14, 2019 - 6:53:07 PM
Last modification on : Wednesday, September 30, 2020 - 8:54:16 AM

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  • HAL Id : hal-02288491, version 1

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LTCI | PARISTECH | INSTITUT-TELECOM | COMELEC | SSH

Citation

Noriyuki Miura, Kohei Matsuda, Karol Myszkowski, Makoto Nagata, Shivam Bhasin, et al.. A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor. Symposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267. ⟨hal-02288491⟩

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