Efficient Data-Flow Analysis of UML/SysML Diagrams for Optimized Model Compilation of Hardware-Software Systems
Abstract
Growing needs in terms of latency, throughput and flexibility are driving the architectures of tomorrow’s Ra- dio Access Networks towards more centralized configurations that rely on cloud-computing paradigms. In these new architectures, digital signals are processed on a large variety of hardware units (e.g., CPUs, Field Programmable Gate Arrays, Graphical Processing Units). Optimizing model compilers that target these archi- tectures must rely on efficient analysis techniques to optimally generate software for signal-processing appli- cations. In this paper, we present a blocking combination of the iterative and worklist algorithms to perform static data-flow analysis on functional views denoted with UML Activity and SysML Block diagrams. We demonstrate the effectiveness of the blocking mechanism with reaching definition analysis of UML/SysML models for a 5G channel decoder (receiver side) and a Software Defined Radio system. We show that sig- nificant reductions in the number of unnecessary visits of the models’ control-flow graphs are achieved, with respect to a non-blocking combination of the iterative and worklist algorithms.