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Conference papers
Physical architectures for packet-switching network nodes based on non-linear logic gates
H. Teimoori
D. Apostolopoulos
K. Vlachos
Cédric Ware
1, 2
D. Petrantonakis
Leontios Stampoulidis
H. Avramopoulos
D. Erasme
1, 2
H. Teimoori
Author
D. Apostolopoulos
Author
K. Vlachos
Author
Cédric Ware 1, 2
Mail :
Author IdHAL : cedric-ware
1
GTO - Télécommunications Optiques (46 rue Barrault
75013 Paris - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (46 rue Barrault F-75634 Paris Cedex 13 - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
2
COMELEC - Département Communications & Electronique (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
Document type :
Conference papers
Domain :
Complete list of metadatas
https://hal.telecom-paris.fr/hal-02411803
Contributor : Telecomparis Hal <>
Submitted on : Sunday, December 15, 2019 - 12:19:01 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:55 PM
Contributor : Telecomparis Hal <>
Submitted on : Sunday, December 15, 2019 - 12:19:01 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:55 PM
Identifiers
- HAL Id : hal-02411803, version 1
Collections
INSTITUT-TELECOM | PARISTECH | COMELEC | GTO | LTCI
Citation
H. Teimoori, D. Apostolopoulos, K. Vlachos, Cédric Ware, D. Petrantonakis, et al.. Physical architectures for packet-switching network nodes based on non-linear logic gates. 6th Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP08, Aug 2008, Graz, Austria. ⟨hal-02411803⟩
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