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Physical architectures for packet-switching network nodes based on non-linear logic gates

H. Teimoori D. Apostolopoulos K. Vlachos Cédric Ware 1, 2 D. Petrantonakis Leontios Stampoulidis H. Avramopoulos D. Erasme 1, 2 
1 GTO - Télécommunications Optiques
LTCI - Laboratoire Traitement et Communication de l'Information
2 COMELEC - Département Communications & Electronique
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Conference papers
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https://hal.telecom-paris.fr/hal-02411803
Contributor : TelecomParis HAL Connect in order to contact the contributor
Submitted on : Sunday, December 15, 2019 - 12:19:01 PM
Last modification on : Tuesday, October 19, 2021 - 11:14:21 AM

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  • HAL Id : hal-02411803, version 1

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INSTITUT-TELECOM | PARISTECH | LTCI | COMELEC | GTO

Citation

H. Teimoori, D. Apostolopoulos, K. Vlachos, Cédric Ware, D. Petrantonakis, et al.. Physical architectures for packet-switching network nodes based on non-linear logic gates. 6th Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP08, Aug 2008, Graz, Austria. ⟨hal-02411803⟩

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