A Novel Design Methodology for Multiplierless Filters Applied on Delta Sigma Decimators

Abstract : This paper presents a novel methodology to design multiplierless digital filters. It is very simple to implement and allows to optimize the order and the number of adders of the filter. The technique was employed to design two decimators for a 640 MHz-12 bits and a 26 MHz- 13 bits Delta Sigma Analog to Digital converters ( ADCs). The filters were synthesized in a 65 nm CMOS process. Their power consumption and die are are (12.54 mW, 0.075 mm2) for the first decimator and (110.2 W , 0.051 mm2) for the second. This is very well positionned in the state of art and thus proves the efficiency of the proposed methodology.