Design Methodology of an ASIC TRNG based on an open-loop delay chain

Molka Ben Romdhane; Jean-Luc Danger; Tarik Graba; Yves Mathieu

doi:10.1109/NEWCAS.2013.6573654

Conference papers

Design Methodology of an ASIC TRNG based on an open-loop delay chain

Molka Ben Romdhane ^{1, 2} Jean-Luc Danger ^{1, 2} Tarik Graba ^{1, 2} Yves Mathieu ^{1, 2}

1 SSH - Secure and Safe Hardware

LTCI - Laboratoire Traitement et Communication de l'Information

2 COMELEC - Département Communications & Electronique

Keywords : TRNG ASIC FPGA AIS-31

Document type :

Conference papers

Domain :

Engineering Sciences [physics] / Electronics

Complete list of metadatas

https://hal.telecom-paris.fr/hal-02411986
Contributor : Telecomparis Hal <>
Submitted on : Sunday, December 15, 2019 - 12:40:31 PM
Last modification on : Wednesday, September 30, 2020 - 8:54:16 AM

Design Methodology of an ASIC TRNG based on an open-loop delay chain

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Design Methodology of an ASIC TRNG based on an open-loop delay chain

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