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FPGA design of an Open-Loop True Random Number Generator

Florent Lozac'H 1, 2 Molka Ben Romdhane 1, 2 Tarik Graba 1, 2 Jean-Luc Danger 1, 2
1 SSH - Secure and Safe Hardware
LTCI - Laboratoire Traitement et Communication de l'Information
Abstract : This paper presents the design methodology of a metastability-based True Random Number Generator (TRNG) on a Xilinx FPGA. As its structure is based on an open-loop delay chain, it provides both high throughput and security against physical attacks since it is not sensitive to coupling attacks as for oscillator-based TRNG. The proposed architecture, implemented in a Virtex-5 XC5VLX50T, uses 4% of the available resources and generates random bits at a 20 Mbps rate. This work gives a detailed description of the design methodology, more specifically the placement, routing and timing analysis of the TRNG structure. Also, the randomness quality of this TRNG has been validated using AIS-31 and NIST statistical tests
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https://hal.telecom-paris.fr/hal-02412025
Contributor : Telecomparis Hal <>
Submitted on : Sunday, December 15, 2019 - 12:42:13 PM
Last modification on : Wednesday, September 30, 2020 - 8:54:16 AM

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Florent Lozac'H, Molka Ben Romdhane, Tarik Graba, Jean-Luc Danger. FPGA design of an Open-Loop True Random Number Generator. 16th euromicro conference on digital system design, Sep 2013, Santander, Spain. pp.615-622, ⟨10.1109/DSD.2013.73⟩. ⟨hal-02412025⟩

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