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Conference papers
Efficient Computation of Combinational Circuits Reliability Based on Probabilistic Transfer Matrix
Lirida Alves de Barros Naviner 1, 2
Author
Kaikai Liu 1, 2
Author
Hao Cai 1, 2
Author
Jean-François Naviner
Author
1
SSH - Secure and Safe Hardware (46 rue Barrault
75013 Paris - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (46 rue Barrault F-75634 Paris Cedex 13 - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
2
COMELEC - Département Communications & Electronique (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
Complete list of metadatas
https://hal.telecom-paris.fr/hal-02412060
Contributor : Telecomparis Hal <>
Submitted on : Sunday, December 15, 2019 - 12:43:43 PM
Last modification on : Wednesday, January 8, 2020 - 1:06:05 AM
Contributor : Telecomparis Hal <>
Submitted on : Sunday, December 15, 2019 - 12:43:43 PM
Last modification on : Wednesday, January 8, 2020 - 1:06:05 AM
Identifiers
- HAL Id : hal-02412060, version 1
Collections
PARISTECH | COMELEC | SSH | LTCI | INSTITUT-TELECOM
Citation
Lirida Alves de Barros Naviner, Kaikai Liu, Hao Cai, Jean-François Naviner. Efficient Computation of Combinational Circuits Reliability Based on Probabilistic Transfer Matrix. International Conference on IC Design and Technology (ICICDT), May 2014, Austin, United States. ⟨hal-02412060⟩
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