Reliability-aware Delay Faults Evaluation of CMOS Flip-Flops

Hao Cai; Kaikai Liu; Lirida Alves de Barros Naviner

Conference papers

Reliability-aware Delay Faults Evaluation of CMOS Flip-Flops

Hao Cai ^{1, 2} Kaikai Liu ^{1, 2} Lirida Alves de Barros Naviner ^{1, 2}

1 SSH - Secure and Safe Hardware

LTCI - Laboratoire Traitement et Communication de l'Information

2 COMELEC - Département Communications & Electronique

Document type :

Conference papers

Domain :

Engineering Sciences [physics] / Micro and nanotechnologies/Microelectronics

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https://hal.telecom-paris.fr/hal-02412061
Contributor : Telecomparis Hal <>
Submitted on : Sunday, December 15, 2019 - 12:43:45 PM
Last modification on : Wednesday, September 30, 2020 - 8:54:16 AM

Reliability-aware Delay Faults Evaluation of CMOS Flip-Flops

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Reliability-aware Delay Faults Evaluation of CMOS Flip-Flops

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