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Conference papers
Side-channel leakage on silicon substrate of CMOS cryptographic chip
Daisuke Fujimoto
Daichi Tanaka
Noriyuki Miura
Makoto Nagata
Yu-Ichi Hayashi
Naofumi Homma
1, 2
Shivam Bhasin
1, 2
Jean-Luc Danger
1, 2
Yu-Ichi Hayashi
Author
Naofumi Homma 1, 2
Author
Shivam Bhasin 1, 2
Author
Jean-Luc Danger 1, 2
Mail : Site :
Author IdHAL : jeanluc-danger
1
SSH - Secure and Safe Hardware (46 rue Barrault
75013 Paris - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (46 rue Barrault F-75634 Paris Cedex 13 - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
2
COMELEC - Département Communications & Electronique (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
Domain :
Complete list of metadatas
https://hal.telecom-paris.fr/hal-02412069
Contributor : Telecomparis Hal <>
Submitted on : Sunday, December 15, 2019 - 12:44:14 PM
Last modification on : Wednesday, January 8, 2020 - 1:55:15 AM
Contributor : Telecomparis Hal <>
Submitted on : Sunday, December 15, 2019 - 12:44:14 PM
Last modification on : Wednesday, January 8, 2020 - 1:55:15 AM
Identifiers
- HAL Id : hal-02412069, version 1
- DOI : 10.1109/HST.2014.6855564
Collections
INSTITUT-TELECOM | COMELEC | SSH | LTCI | PARISTECH
Citation
Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-Ichi Hayashi, et al.. Side-channel leakage on silicon substrate of CMOS cryptographic chip. HOST, May 2014, Washington DC, United States. ⟨10.1109/HST.2014.6855564⟩. ⟨hal-02412069⟩
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