Side-channel leakage on silicon substrate of CMOS cryptographic chip

Daisuke Fujimoto; Daichi Tanaka; Noriyuki Miura; Makoto Nagata; Yu-Ichi Hayashi; Naofumi Homma; Shivam Bhasin; Jean-Luc Danger

doi:10.1109/HST.2014.6855564

Conference papers

Side-channel leakage on silicon substrate of CMOS cryptographic chip

Daisuke Fujimoto Daichi Tanaka Noriyuki Miura Makoto Nagata Yu-Ichi Hayashi Naofumi Homma ^{1, 2} Shivam Bhasin ^{1, 2} Jean-Luc Danger ^{1, 2}

1 SSH - Secure and Safe Hardware

LTCI - Laboratoire Traitement et Communication de l'Information

2 COMELEC - Département Communications & Electronique

Document type :

Conference papers

Domain :

Engineering Sciences [physics] / Electronics

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Submitted on : Sunday, December 15, 2019 - 12:44:14 PM
Last modification on : Thursday, November 18, 2021 - 1:02:02 PM

Side-channel leakage on silicon substrate of CMOS cryptographic chip

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Side-channel leakage on silicon substrate of CMOS cryptographic chip

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