A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement

Daisuke Fujimoto; Makoto Nagata; Shivam Bhasin; Jean-Luc Danger

doi:10.1109/ASPDAC.2015.7059100

Conference papers

A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement

Daisuke Fujimoto Makoto Nagata Shivam Bhasin ^{1, 2} Jean-Luc Danger ^{1, 2}

1 SSH - Secure and Safe Hardware

LTCI - Laboratoire Traitement et Communication de l'Information

2 COMELEC - Département Communications & Electronique

Document type :

Conference papers

Domain :

Computer Science [cs] / Cryptography and Security [cs.CR]

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Submitted on : Sunday, December 15, 2019 - 12:52:10 PM
Last modification on : Thursday, November 18, 2021 - 1:02:02 PM

A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement

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A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement

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