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A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement

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https://hal.telecom-paris.fr/hal-02412244
Contributor : Telecomparis Hal Connect in order to contact the contributor
Submitted on : Sunday, December 15, 2019 - 12:52:10 PM
Last modification on : Thursday, November 18, 2021 - 1:02:02 PM

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Daisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger. A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. ASP-DAC, Jan 2015, Tokyo, Japan. ⟨10.1109/ASPDAC.2015.7059100⟩. ⟨hal-02412244⟩

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