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High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

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https://hal.telecom-paris.fr/hal-02517649
Contributor : Tarik Graba <>
Submitted on : Tuesday, March 24, 2020 - 4:50:34 PM
Last modification on : Friday, July 31, 2020 - 11:28:08 AM

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Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, et al.. High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2020, 69 (4), pp.534-548. ⟨10.1109/TC.2019.2957355⟩. ⟨hal-02517649⟩

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