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Journal articles
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
Rei Ueno
1
Naofumi Homma
1
Sumio Morioka
2
Noriyuki Miura
3
Kohei Matsuda
3
Makoto Nagata
3
Shivam Bhasin
4
Yves Mathieu
5, 6
Tarik Graba
7, 6, 5
Jean-Luc Danger
5, 6
Tarik Graba 7, 6, 5
Author IdHAL : tarikgraba
Jean-Luc Danger 5, 6
Author IdHAL : jeanluc-danger
1
Tohoku University [Sendai] (2-1-1 Katahira, Aoba-ku, Sendai, 980-8577 Japan - Japan)
2
Interstellar Technologies Inc., Hokkaido (Japan)
3
Konan University [Kobe, Japan] (7-1-20 Minatojima-minamimachi, Chuo-ku, Kobe 650-0047 - Japan)
4
Nanyang Technological University [Singapour] (50 Nanyang Ave, Singapour 639798 - Singapore)
5
SSH - Secure and Safe Hardware (Télécom Paris 19 Place Marguerite Perey 91120 Palaiseau - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (Télécom Paris 19 Place Marguerite Perey 91120 PALAISEAU - France)
- Télécom Paris (19 Place Marguerite Perey 91120 Palaiseau - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
6
COMELEC - Département Communications & Electronique (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
7
LTCI - Laboratoire Traitement et Communication de l'Information (Télécom Paris 19 Place Marguerite Perey 91120 PALAISEAU - France)
- Télécom Paris (19 Place Marguerite Perey 91120 Palaiseau - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
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Journal articles
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https://hal.telecom-paris.fr/hal-02517649
Contributor : Tarik Graba <>
Submitted on : Tuesday, March 24, 2020 - 4:50:34 PM
Last modification on : Tuesday, September 21, 2021 - 2:16:05 PM
Contributor : Tarik Graba <>
Submitted on : Tuesday, March 24, 2020 - 4:50:34 PM
Last modification on : Tuesday, September 21, 2021 - 2:16:05 PM
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- HAL Id : hal-02517649, version 1
- DOI : 10.1109/TC.2019.2957355
Citation
Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, et al.. High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2020, 69 (4), pp.534-548. ⟨10.1109/TC.2019.2957355⟩. ⟨hal-02517649⟩
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