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High Throughput and Low Power Enhancements for LDPC Decoders

Abstract : Modern VLSI decoders for low-density parity- check (LDPC) codes require high throughput performance while achieving high energy efficiency on the smallest possible foot- print. In this paper, we present two optimizations to enhance the throughput and reduce the power consumption for these decoders. As a first optimization, we seek to speedup the decoding task by modifying the processing step known as syndrome check. We partition this task and perform it in on-the-fly fashion. As a second optimization, we address the topic of iteration control in order to save energy and time on unnecessary decoder operation when processing undecodable blocks. We propose an iteration control policy that is driven by the combination of two decision metrics. Furthermore, we show empirically how stopping criteria should be tuned as a function of false alarm and missed detection rates. Throughout this paper we use the codes defined in the IEEE 802.11n standard to show performance results of the proposed optimizations.
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Contributor : Renaud Pacalet Connect in order to contact the contributor
Submitted on : Wednesday, July 8, 2020 - 8:45:38 AM
Last modification on : Friday, November 13, 2020 - 11:12:01 AM


  • HAL Id : hal-02893085, version 1


Erick Amador, Raymond Knopp, Renaud Pacalet, Vincent Rezard. High Throughput and Low Power Enhancements for LDPC Decoders. International Journal On Advances in Telecommunications, IARIA, 2011, 4 (1-2), pp.143-155. ⟨hal-02893085⟩



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