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Hardware Optimized Sample Rate Conversion for Software Defined Radio

Raymond Knopp 1 Carina Schmidt-Knorreck 1 Renaud Pacalet 2, 3
3 LabSoC - System on Chip
LTCI - Laboratoire Traitement et Communication de l'Information
Abstract : The evolution towards applications with increasing functionalities leads to the need of high flexible systems that support a high number of different standards while decreasing the required hardware space. Therefore a high configurable platform being able to handle a multitude of standards is needed. One main issue is the tradeoff between performance and space consumption. We present a generic, flexible, fractional and hardware optimized SRC architecture in the context of SDR, providing one architecture to process up to 8 different complex channels. The solution is based on bandlimited interpolation and allows processing by supporting a 1Hz resolution of the sampling rates.
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https://hal.telecom-paris.fr/hal-02893096
Contributor : Renaud Pacalet <>
Submitted on : Wednesday, July 8, 2020 - 9:00:56 AM
Last modification on : Tuesday, September 21, 2021 - 2:16:04 PM

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  • HAL Id : hal-02893096, version 1

Citation

Raymond Knopp, Carina Schmidt-Knorreck, Renaud Pacalet. Hardware Optimized Sample Rate Conversion for Software Defined Radio. Frequenz Journal of RF-Engineering and Telecommunications, 2010. ⟨hal-02893096⟩

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