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Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors

Abstract : Many of the pitfalls in side-channel-resistant hardware design can be avoided using the right methodology and a systematic design flow. The authors present the back end of such a design flow and show a solution that combines a specialized cell library with a dedicated place-and-route method.
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https://hal.telecom-paris.fr/hal-02893104
Contributor : Renaud Pacalet <>
Submitted on : Wednesday, July 8, 2020 - 9:05:04 AM
Last modification on : Friday, October 16, 2020 - 4:19:35 PM

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Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu. Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. IEEE Design & Test of Computers, Institute of Electrical and Electronics Engineers, 2007, 24 (6), pp.546-555. ⟨10.1109/MDT.2007.202⟩. ⟨hal-02893104⟩

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