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Poster communications

Interactive System Level Debugging of Systems-on-Chip

Abstract : Hardware architecture is modeled using generic hardware components (CPUs, buses, hardware accelerators) (1) Application Modelling System is modeled in terms of communicating tasks (UML class diagram) Behavior modeling is focused on control part of the application (UML activity diagrams) (3) Application mapped onto an architecture Refinement Simulation Formal static analysis Fast transaction-based simulation For further information: An open-source toolkit-called TTool-fully supports this methodology. Computation and communication events are represented by symbolic instructions and span potentially hundreds of clock cycles Simulation granularity automatically adapts to the granularity of the application Instructions are executed as a whole if possible, they may be broken down into several transactions due to inter-task synchronization Fully implemented in C++, possibility to generate traces in VCD format Possibility to save and restore simulation states Interaction of Frontend and Simulator Simulator Design Execution HW Discrete Event Simulator Task model For a car communication application, we achieved an order of magnitude of simulation speed of Billions of cycles/sec. A more fine grained model of an MPEG decoder led to a rate of Millions cycles/sec. Abstract Channels Communication HW Transaction: Start Time Virtual Length [Ex. units] Length [Time units]
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Contributor : Renaud Pacalet <>
Submitted on : Thursday, July 16, 2020 - 8:39:03 AM
Last modification on : Sunday, August 2, 2020 - 4:53:53 AM


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  • HAL Id : hal-02893131, version 1


Daniel Knorreck, Ludovic Apvrille, Renaud Pacalet. Interactive System Level Debugging of Systems-on-Chip. S4D, Sep 2010, Southampton, United Kingdom. ⟨hal-02893131⟩



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