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Dynamic Power Management on LDPC Decoders

Abstract : This paper presents a dynamic power management strategy for the iterative decoding of low-density parity-check (LDPC) codes. We propose an online algorithm for adjusting the operation of a power manageable decoder. Decision making is based upon the monitoring of a convergence metric independent from the message computation kernel. Furthermore we analyze the feasibility of a VLSI implementation for such algorithm. Up to 54% savings in energy were achieved with a relatively low loss on error-correcting performance.
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https://hal.telecom-paris.fr/hal-02893140
Contributor : Renaud Pacalet <>
Submitted on : Wednesday, July 8, 2020 - 9:29:35 AM
Last modification on : Friday, November 13, 2020 - 11:12:01 AM

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Erick Amador, Raymond Knopp, Vincent Rezard, Renaud Pacalet. Dynamic Power Management on LDPC Decoders. 2010 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2010, Lixouri, France. pp.416-421, ⟨10.1109/ISVLSI.2010.70⟩. ⟨hal-02893140⟩

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