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Hardware Optimized Sample Rate Conversion for Software Defined Radio

Carina Schmidt-Knorreck 1 Raymond Knopp 1 Renaud Pacalet 2, 3 
3 LabSoC - System on Chip
LTCI - Laboratoire Traitement et Communication de l'Information
Abstract : The evolution towards applications with increasing functionalities leads to the need of high flexible systems that support a high number of different standards while decreasing the required hardware space. Therefore a high configurable platform being able to handle a multitude of standards is needed. One main issue is the tradeoff between performance and space consumption. We present a generic, flexible, fractional and hardware optimized SRC architecture in the context of SDR, providing one architecture to process up to 8 different complex channels. The solution is based on bandlimited interpolation and allows processing by supporting a 1Hz resolution of the sampling rates.
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Contributor : Renaud Pacalet Connect in order to contact the contributor
Submitted on : Wednesday, July 8, 2020 - 9:38:23 AM
Last modification on : Tuesday, October 19, 2021 - 11:15:20 AM


  • HAL Id : hal-02893158, version 1


Carina Schmidt-Knorreck, Raymond Knopp, Renaud Pacalet. Hardware Optimized Sample Rate Conversion for Software Defined Radio. WSR 2010, 6th Karlsruhe Workshop on Software Radios, Mar 2010, Karlsruhe, Germany. ⟨hal-02893158⟩



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