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Optimum LDPC Decoder: A Memory Architecture Problem

Abstract : This paper addresses a frequently overlooked problem: de- signing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.
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Contributor : Renaud Pacalet <>
Submitted on : Wednesday, July 8, 2020 - 9:44:59 AM
Last modification on : Thursday, September 24, 2020 - 3:24:44 PM



Erick Amador, Renaud Pacalet, Vincent Rezard. Optimum LDPC Decoder: A Memory Architecture Problem. the 46th Annual Design Automation Conference, Jul 2009, San Francisco, France. pp.891, ⟨10.1145/1629911.1630141⟩. ⟨hal-02893173⟩



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