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Fast Simulation Techniques for Design Space Exploration

Abstract : This paper addresses a UML based toolkit for performing e cient system-level design space exploration of System-On-Chip. An innovative simulation strategy to significantly reduce simulation time is introduced. The basic idea is to take benefit from high level descriptions of applications by processing transactions spanning potentially hundreds of clock cycles as a whole. When a need for inter task synchronization arises, transactions may be split into smaller chunks. The simulation engine is therefore predictive and supports backward execution thanks to transaction truncation. Thus, simulation granularity adapts automatically to application requirements. This paper also highlights the benefits of TTool, an open-source toolkit that fully integrates the aforementioned simulation engine. Emphasis is more particularly put on procedures taking place under the hood after having pushed the simulation button of the tool. Finally, the new simulation strategy is assessed and compared to an earlier cycle-based version of the simulation engine.
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https://hal.telecom-paris.fr/hal-02893190
Contributor : Renaud Pacalet <>
Submitted on : Wednesday, July 8, 2020 - 9:54:22 AM
Last modification on : Tuesday, September 21, 2021 - 2:16:04 PM
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  • HAL Id : hal-02893190, version 1

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Daniel Knorreck, Ludovic Apvrille, Renaud Pacalet. Fast Simulation Techniques for Design Space Exploration. International Conference on Objects, Components, Models and Patterns (TOOLS EUROPE 2009), 2009, Zurich, Switzerland. ⟨hal-02893190⟩

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