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Evaluation of ASIPs Design with LISATek

Rashid Muhammad 1, 2 Ludovic Apvrille 1, 2 Renaud Pacalet 1, 2
1 LabSoC - System on Chip
LTCI - Laboratoire Traitement et Communication de l'Information
Abstract : This paper evaluates an ASIP design methodology based on the extension of an existing instruction set and architecture described with LISA 2.0 language. The objective is to accelerate the ASIPs design process by using partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of ISE (Instruction Set Extension) techniques. A case study demonstrates the methodological approach for the JPEG algorithm.
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https://hal.telecom-paris.fr/hal-02893215
Contributor : Renaud Pacalet <>
Submitted on : Wednesday, July 8, 2020 - 10:07:48 AM
Last modification on : Friday, October 16, 2020 - 4:19:21 PM

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Rashid Muhammad, Ludovic Apvrille, Renaud Pacalet. Evaluation of ASIPs Design with LISATek. 8th International Workshop SAMOS, Jul 2008, Samos, Greece. pp.177-186, ⟨10.1007/978-3-540-70550-5_20⟩. ⟨hal-02893215⟩

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