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Conference papers

CMOS structures suitable for secured hardware

S. Guilley 1, 2 P. Hoogvorst 1, 2 y. Mathieu 1, 2 Renaud Pacalet 1, 2 J. Provost 1, 2 
1 GET-Télécom Paris
2 LTCI - Laboratoire Traitement et Communication de l'Information
Abstract : Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.
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Conference papers
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https://hal.telecom-paris.fr/hal-02893279
Contributor : Renaud Pacalet Connect in order to contact the contributor
Submitted on : Wednesday, July 8, 2020 - 10:32:40 AM
Last modification on : Friday, October 16, 2020 - 4:38:33 PM

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INSTITUT-TELECOM | CNRS | PARISTECH | TDS-MACS | LTCI | COMELEC | LABSOC | SSH

Citation

S. Guilley, P. Hoogvorst, y. Mathieu, Renaud Pacalet, J. Provost. CMOS structures suitable for secured hardware. Design, Automation and Test in Europe Conference and Exhibition, Feb 2004, Paris, France. pp.1414-1415, ⟨10.1109/DATE.2004.1269113⟩. ⟨hal-02893279⟩

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