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CMOS structures suitable for secured hardware

Abstract : Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.
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Contributor : Renaud Pacalet Connect in order to contact the contributor
Submitted on : Wednesday, July 8, 2020 - 10:32:40 AM
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S. Guilley, P. Hoogvorst, y. Mathieu, Renaud Pacalet, J. Provost. CMOS structures suitable for secured hardware. Design, Automation and Test in Europe Conference and Exhibition, Feb 2004, Paris, France. pp.1414-1415, ⟨10.1109/DATE.2004.1269113⟩. ⟨hal-02893279⟩



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