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Communication Dans Un Congrès Année : 1997

A VLSI architecture for image geometrical transformations using an embedded core based processor

Résumé

This paper presents a circuit dedicated to real time geometrical transforms of pictures. The supported transforms are third degree polynomials of two variables. The post-processing is performed by a bilinear filter. An embedded DSP core is in charge of high level, low rate, control tasks while a set of hard wired units is in charge of computing intensive low level tasks.
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Dates et versions

hal-02893298 , version 1 (08-07-2020)

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Citer

C. Miro, N. Darbel, Renaud Pacalet, V. Paquet. A VLSI architecture for image geometrical transformations using an embedded core based processor. IEEE International Conference on Application-Specific Systems, Architectures and Processors, Jul 1997, Zurich, France. pp.86-95, ⟨10.1109/ASAP.1997.606815⟩. ⟨hal-02893298⟩
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