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A VLSI architecture for image geometrical transformations using an embedded core based processor

C. Miro 1 N. Darbel 1 Renaud Pacalet 1 V. Paquet 1
1 ENST - Ecole Nationale Supérieure des Télécommunications
Abstract : This paper presents a circuit dedicated to real time geometrical transforms of pictures. The supported transforms are third degree polynomials of two variables. The post-processing is performed by a bilinear filter. An embedded DSP core is in charge of high level, low rate, control tasks while a set of hard wired units is in charge of computing intensive low level tasks.
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Conference papers
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https://hal.telecom-paris.fr/hal-02893298
Contributor : Renaud Pacalet <>
Submitted on : Wednesday, July 8, 2020 - 10:43:42 AM
Last modification on : Sunday, August 2, 2020 - 4:53:53 AM

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PARISTECH | INSTITUT-TELECOM

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C. Miro, N. Darbel, Renaud Pacalet, V. Paquet. A VLSI architecture for image geometrical transformations using an embedded core based processor. IEEE International Conference on Application-Specific Systems, Architectures and Processors, Jul 1997, Zurich, France. pp.86-95, ⟨10.1109/ASAP.1997.606815⟩. ⟨hal-02893298⟩

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