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Constraint programming for design space exploration of dataflow applications on multi-bus architectures

Abstract : This thesis is part of a collaboration between Télécom Paris and Nokia Bell Labs France. In this context, we focus on the system-level Design Space Exploration of embedded systems for the execution of signal processing applications. In the system we target, the design space exploration process intends to identify the allocation and scheduling of both application tasks and data transfers between these tasks: this identification plays a key role in the overall performance (e.g. end-to-end latency) of these systems. While there are already multiple works for diverse communication architectures, this thesis focuses on multi-bus architectures that are particularly well-suited for computation platforms of signal processing applications. For these platforms, we show that only limited contributions have already been proposed. Three contributions are proposed to tackle the above mentioned problem. 1) A satisfiability modulo theories (SMT) formulation which allows to explore mapping and scheduling decisions on multi-bus architectures for latency optimization; We demonstrate its ability to produce a solution for well-known applications. Yet, 2) to mitigate the scalability limitations for the optimal solution search of this first contribution, we propose a technique to prune the design space of searched solutions. Evaluations we provide demonstrate a better scalability. Last, 3) communication allocation is enhanced with power consumption, and we show how to jointly optimize latency and power consumption. Our evaluation is again applied to a set of well-known signal processing applications and demonstrates how different trade-offs between latency and power consumption can be studied.Our contributions are integrated into a state-of-the-art modeling and verification tool for the system-level design of embedded systems (TTool). Perspectives are articulated in mainly two axes. 1) Extending the current formulation to account for new design aspects (e.g., shared memory, throughput). 2) Further improving the scalability of the optimal search.
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Submitted on : Thursday, January 6, 2022 - 5:35:08 PM
Last modification on : Friday, January 7, 2022 - 3:06:23 AM


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  • HAL Id : tel-03515492, version 1


Amna Gharbi. Constraint programming for design space exploration of dataflow applications on multi-bus architectures. Hardware Architecture [cs.AR]. Institut Polytechnique de Paris, 2021. English. ⟨NNT : 2021IPPAT018⟩. ⟨tel-03515492⟩



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