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Circuit-level Hardening Against Multiple Faults: Combining Global TMR and Selective Hardening

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https://hal.telecom-paris.fr/hal-02286728
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 4:06:09 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:53 PM

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  • HAL Id : hal-02286728, version 1

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Samuel Nascimento Pagliarini, Lirida Alves de Barros Naviner, Jean-François Naviner. Circuit-level Hardening Against Multiple Faults: Combining Global TMR and Selective Hardening. Journées Nationales du Réseau Doctoral de Microélectronique, Jun 2013, Grenoble, France. ⟨hal-02286728⟩

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