Circuit-level Hardening Against Multiple Faults: Combining Global TMR and Selective Hardening - Archive ouverte HAL Access content directly
Conference Papers Year : 2013

Circuit-level Hardening Against Multiple Faults: Combining Global TMR and Selective Hardening

Domains

Engineering Sciences [physics] Micro and nanotechnologies/Microelectronics Engineering Sciences [physics] Electronics

TelecomParis HAL  : Connect in order to contact the contributor

https://hal.telecom-paris.fr/hal-02286728

Submitted on : Friday, September 13, 2019-4:06:09 PM

Last modification on : Tuesday, February 28, 2023-3:36:23 PM

Not file

Dates and versions

hal-02286728 , version 1 (13-09-2019)

Identifiers

  • HAL Id : hal-02286728 , version 1

Cite

Samuel Nascimento Pagliarini, Lirida Alves de Barros Naviner, Jean-François Naviner. Circuit-level Hardening Against Multiple Faults: Combining Global TMR and Selective Hardening. Journées Nationales du Réseau Doctoral de Microélectronique, Jun 2013, Grenoble, France. ⟨hal-02286728⟩

Export

BibTeX TEI Dublin Core DC Terms EndNote Datacite

Collections

INSTITUT-TELECOM CNRS PARISTECH LTCI COMELEC SSH
9 View
0 Download

Share

Gmail Facebook Twitter LinkedIn More